Subject: Re: TLB miss and crash
To: John Maier <email@example.com>
From: Maciej W. Rozycki <firstname.lastname@example.org>
Date: 11/28/2002 16:41:37
On Wed, 27 Nov 2002, John Maier wrote:
> There doesn't seem to be much discussion on this...why is this happening and
> what is a TLB miss?
In MIPS processors the TLB (or Translation Lookaside Buffer) is used to
implement paging, i.e. translating virtual addresses as used by programs
(including kernels) to physical addresses as seen on the bus. There are
actually ranges defined for which the translation is done differently, but
that's irrelevant here. The TLB is fully-associative memory of a small
size (small being e.g. 48- or 64-entry, as it is implemented in processors
used by DECstations), that varies across processor models, and does not
cover all pages in a system. If an instruction accessing memory, i.e. a
load or a store, is executed and the processor cannot find a translation
for the virtual address involved in the TLB, this is called a "TLB miss".
When it happens a special predefined procedure (called a "handler") is
called by the processor automatically (the call is named an "exception"),
which, under normal circumstances, does a lookup for a translation in the
system memory, in a place defined by the kernel, and if succeeded it loads
obtained data into the TLB randomly replacing one of the existing entries.
Then it returns and the memory access operation is reexecuted.
If you get a TLB miss report, it means that the exception handler failed
to do retrieve data for a translation for some reason. While knowing the
hardware reasonably, I don't have sufficient knowledge on NetBSD --
hopefully someone else will be able to tell you why the handler fails.
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+ e-mail: email@example.com, PGP key available +