Algorithmics Ltd of UK, one of the coolest MIPS guys on the planet,
provides useful documents online.  Written in 1992, the previous
century, "R4x00 Interface Design Guide" is quite enlightening.  It's
available as;

    http://www.algor.co.uk/ftp/pub/doc/r4k-interface-guide.ps.gz 
    (It's a plain PS file)

The quote from page 6,

---
The CPU pipeline progresses at twice the input clock frequency.  This
means that a processor using a "50MHz" input clock can run
instructions at a peak rate of 100MHz instructions/second.

R4x00 family members differ in pipeline organization; the R4000 has an
8-stage pipeline, while the R4600/R4200 are 5-stage.  At the same
clock rate, the shorter pipeline performs better; the longer pipeline can
improve performance only where it makes higher clock rates possible.

Different suppliers use inconsistent clock-rate suffixes on their
parts.  Some parts are always describted by the pipeline clock rate;
but R4400 parts were traditionary describted by their input clock
rate - don't be deceived, they're not running at half the the speed. 
---

The doco is a-must-read item for MIPS hardware designers, I think.

Tohru Nishimura
Information Technology Centre
Nara Institute of Science and Technology