Only one comment from me.  Building interrupt handler in assembly
would not overcome interrupt latency.

>        -The interrupt load on headed pmax systems is high and
>         heavily blocked.

This is a nightmare .  Every DECstation is designed differently in
interrupt masking.  The makes very hard to implement consistent spl()
across various models.

	PMAX	no brainer design.  Since it is a desktop computer with
		no option card, it brings little trouble.
	3MAX	the first TC option card machine.  The design decision
		was fair and fine mostly.  4MB TC address space was
		just too small and it's anachronistic to have different
		meaning	between R/W ops of interrupt mask register.
	3MIN	a doomed computer.  the first IOASIC machine.  It was a
		100% mistake the designer assigned processor HW
		interrupt signals to 4 different TC slots.  What spl()
		calls do must be adjusted by what kind of TC option cards
		installed in which TC slot.  Say, one might be PMAD-A,
		one PMAGB-B, and another PMAZ-A.  All three are different
		natures and must be cared with differrent spl() scheme.
		The hell was deepened the time when R4000 processor upgrade
		module was implemented. It's very unfortunate, and I would
		call it R4000 processor design caveat, that resetting SR
		value of R4000 with a new one is not atomically safe.
		Depending on a bit combination of IE, EXL and HW/SW INT
		masks, it would allow to post interrupt(s) pending even if
		the reset trys disabled->disabled transition.  This is the
		reason why ULTRIX locore.s has ugly #ifdefs for R4000 3MIN.
	3MAX+	Digital recognized TC option slots should be cared in line
		with IOASIC devices.  Interrupt mask can block TC slots
		as well as onboard devices.  Unfortunately, NetBSD/pmax
		blocks the IOASIC devices entirely when it does spl() for a
		single IOASIC device.
	MAXINE	a replicated decision and the same conclusion.

NetBSD/pmax could not find out a sane solution to cope with the design
inconsistency so far, and does overblocking.

Tohru Nishimura