On Wed, 17 May 2000, David Evans wrote:

> Peter C. Wallace wrote:
> > 
> > 	Looks like (with a quick ohmmeter check) that most if not all
> > MIPS bus signals go through ASIC to the daughterboard connector...
> > 
> 
>   How well does the MIPS bus run over connectors like this?  Perhaps that was
> the reason for the creaiton of a "new" protocol between the CPU mdoule and
> the motherboard.  SGI did a similar thing on the R4000 Indigo and subsequent
> machines, allowing one to stick, say, an R5000 in an Indy that came with a
> cacheless R4600.  They didn't do it with Crimson, their first R4x00 design,
> so maybe they learned from that.  I haven't disected an Onyx/Challenge to see
> how the IP19 CPU boards are set up.
> 
> -- 
> David Evans          (NeXTMail/MIME OK)             dfevans@bbcr.uwaterloo.ca
> PhD Student, Computer/Synth Junkie         http://bbcr.uwaterloo.ca/~dfevans/
> University of Waterloo         "Default is the value selected by the composer
> Ontario, Canada           overridden by your command." - Roland TR-707 Manual
> 

Its actually a good design, all high speed local signals confined to the
daughter-card, once the signals get on the main card, you probably have
much longer signal lengths. 

Peter Wallace