On Fri, 25 Feb 2000, Simon Burge wrote:

> >  There is full documentation on the PixelVision architecture available. 
> > The architecture was first implemented in the SFB adapter.  Documents can
> > be obtained from: 
> >
> > ftp://gatekeeper.dec.com/pub/DEC/SRC/technical-notes/SRC-1998-013.*
> 
> The SFB was the "Smart Frame Buffer" described in the WRL TR93/1 tech
> note (I don't a have URL handy), and was on the PMAGB cards (known

 Not that despite of what one might assume at the first moment, the
document I refer to actually predates TR93/1.  Go and check yourself, if
you don't believe (and that's version 4.0; surely there must have been
earlier ones as well!).

> as SFB as well).  I think this document describes the engine of the
> PMAG-{C,D,E,F} cards (known as PX).  Useful info all the same!

 PX series of cards is based on the PixelStamp architecture, the
predecessor of PixelVision.  PixelStamp documentation was never published,
AFAIK.

> We do have support for both chipsets in NetBSD but unaccelerated in each
> case.  Andy Doran will correct any mistakes about the PX support, I'm
> sure :-)

 I suppose having documentation for the accelerator is more important than
for the frame buffer -- reverse engineering of card layout is surely
easier than of chip internals.  Just my opinion, though.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +