> > +       lw      k0, TF_BASE+TF_REG_EPC(sp)
> >         mtc0    a0, MIPS_COP_0_STATUS
> >         mtlo    t0
> >         mthi    t1
> > -       lw      k0, TF_BASE+TF_REG_EPC(sp)
> >         ...
> >         j       k0
> > 	rfe
> > 	
> > The 'mtc0 a0, ...' insn has the effect to make sure no more interrupt.
> > But if the new code sequence got an interrupt after 'lw k0, ...'
> > before 'mtc0 a0, ...', k0 would be trashed by the interrupt handler
> > (not by mtlo/mthi insns) and glok in a hidious way.  How is this
> > senario?

Oh yeah, that's a bug all right. I've worked on (and fixed) debug stubs
that made this sort of mistake.

>   I think is is very likely, and I also have seen some comments in the
> code that indicate that it may take 1 or 2 clock cycles after the mtc0
> instruction before the interrrupts are actually disabled (but I don't
> know of any documented information on that).

I do. It was in at least one of the MIPS books that I checked last night
while researching my reply about k0/k1.

Todd Whitesel
toddpw @ best.com