Subject: Re: k0/k1 register while mulhi/mullo manipulation
To: None <nisimura@itc.aist-nara.ac.jp>
From: Noriyuki Soda <soda@sra.co.jp>
List: port-pmax
Date: 02/23/2000 20:45:24 
> I noticed my failure to mention to an important point.  PLS add,
> 
> "(Even) when CPU is running kernel mode and no TLB miss is expected,"

Please note, for example, buffer cache is accessed via TLB.
It is dangerous to use k0/k1, even if it is kernel mode.
--
soda