On Wed, 10 Nov 1999, Toru Nishimura wrote:

> One possiblity is pmap_release() was mistakenly called for a live
> process (not a dying process), then ->pm_segtab was assigned with
> value NULL.  But, this theory would not explain symptoms found with
> MIPS1-only kernels.
> 
> My MAXINE still keeps running doing 'libc make' with load averages
> near 5.0.  (I started wondering some of TLB related CP0 registers
> have bogus values in some generation of R3000 processors...)

  I'd bet this is probably the root of the problem.  I think the 3100 has
an R2000A CPU (which I think identifies itself as an R3000).  Later models
probably would have a "real" R3000 CPU.

  I'm not certain what the actual CPU is in my 5000/200 and 5000/25
without opening up the boxes.  The 5000/200 displays "CPU Rev. 2.0 with
MIPS R3010 FPC Rev. 2.0", while the 5000/25 displays "CPU Rev. 3.0 with
MIPS R3010 FPC Rev. 4.0".

  Also, I modified the two places in trap.c to "undo" the MIPS1-only code,
and I was able to boot that kernel on my 5000/200 without any problems.

--- /c/work/src/sys/arch/mips/mips/trap.c       Sat Oct 30 10:41:26 1999
+++ /usr/staff/mhitch/sys/arch/mips/mips/trap.c Tue Nov  9 21:48:21 1999
@@ -459,7 +459,7 @@
                        }
                        entry |= mips_pg_m_bit();
                        pte->pt_entry = entry;
-#if defined(MIPS1) && !defined(MIPS3)
+#if !defined(MIPS1) && !defined(MIPS3)
                        MachTLBUpdate(~0, entry);       /* use entryhi */
 #else
                        vaddr &= ~PGOFSET;
@@ -496,7 +496,7 @@
                }
                entry |= mips_pg_m_bit();
                pte->pt_entry = entry;
-#if defined(MIPS1) && !defined(MIPS3)
+#if !defined(MIPS1) && !defined(MIPS3)
                MachTLBUpdate(~0, entry);               /* use entryhi */
 #else
                vaddr = (vaddr & ~PGOFSET) |


--
Michael L. Hitch			mhitch@montana.edu
Computer Consultant
Information Technology Center
Montana State University	Bozeman, MT	USA