Simon Burge <simonb@netbsd.org> writes:
> I've done a bit of digging, and if I revert this part of the mips jumbo
> patch from September 25, all is ok again on my R4400 5000/260:
> 
> 	Index: mips/pmap.c
> 	===================================================================
> 	RCS file: /cvsroot/syssrc/sys/arch/mips/mips/pmap.c,v
> 	retrieving revision 1.70
> 	retrieving revision 1.71
> 	diff -p -u -w -r1.70 -r1.71
> 	--- pmap.c      1999/09/12 01:17:12     1.70
> 	+++ pmap.c      1999/09/25 00:00:39     1.71
> 	@@ -1197,13 +1197,8 @@ pmap_enter(pmap, va, pa, prot, wired, ac
> 			/* enter entries into kernel pmap */
> 			pte = kvtopte(va);
> 	 
> 	-               /*
> 	-                * XXX more thought... what does ROPAGE mean here?
> 	-                * is it correc to set all the ROPAGE bits for mips3,
> 	-                * but just the valid (and not read-only) bit on mips1?
> 	-                */
> 			if (CPUISMIPS3)
> 	-                       npte |= vad_to_pfn(pa) | MIPS3_PG_ROPAGE | MIPS3_PG_G;
> 	+                       npte |= vad_to_pfn(pa) | MIPS3_PG_G;
> 			else
> 				npte |= vad_to_pfn(pa) | MIPS1_PG_V | MIPS1_PG_G;
> 	 
> 
> 
> Shin - was this needed for hpcmips to work?

(All description assumes options MIPS3 and options MIPS3_L2CACHE_ABSENT.)

In pmap_enter(), npte is initialized as
	npte = mips_pg_ropage_bit();
or
	npte = mips_pg_rwpage_bit();
or
	npte = mips_pg_cwpage_bit();
(if PAGE_IS_MANAGED(pa)).

Then, in pmap_enter_pv(), cache attribute of npte is changed to
MIPS3_PG_UNCACHED when necessary (to avoid virtual alias).

After that, if you modify 'npte' as
	npte |= vad_to_pfn(pa) | MIPS3_PG_ROPAGE | MIPS3_PG_G;
, cache attribute is overwritten by MIPS3_PG_ROPAGE(== MIPS3_PG_V |
MIPS3_PG_RO | MIPS3_PG_CACHED).
              ===============
[1] Therefore, it is wrong to set MIPS3_PG_CACHED in 'npte'.

And, the only difference between mips_pg_ropage_bit() and
mips_pg_cwpage_bit() is whether MIPS3_PG_RO is set or not.

#define	MIPS3_PG_ROPAGE	(MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED)
#define	MIPS3_PG_CWPAGE	(MIPS3_PG_V | MIPS3_PG_CACHED)

If you set MIPS3_PG_RO in 'npte', you can't distinguish
mips_pg_ropage_bit() and mips_pg_cwpage_bit().

[2] Therfore, it is wrong to set MIPS3_PG_RO in 'npte'.

Because of [1] and [2], I changed the line from
			npte |= vad_to_pfn(pa) | MIPS3_PG_ROPAGE | MIPS3_PG_G;
to
			npte |= vad_to_pfn(pa) | MIPS3_PG_G;
.

Anyway, I can't see the relationship between
	MIPS3_PG_RO is set or not in kernel pte
                                     ======
and
	random core dump of user process
.

Takao Shinohara