Subject: Re: TLB manager for devices -- Re: CVS commit: src
To: Toru Nishimura <email@example.com>
From: Andy Doran <firstname.lastname@example.org>
Date: 04/26/1999 13:09:50
On Mon, 26 Apr 1999, Toru Nishimura wrote:
> >> To support the i860 properly, we need a TLB manager and the
> >> right ucode for the damn thing.
> > Special TLB management framework will be required ultimately to
> > support the variety of devices found in Alpha/DECstations (think about
> > R4000 and Alpha TLB)
> NetBSD/mips common code leaves 6 entry of R3000 hard-wired TLBs for no
> purpose. These can over upto 24KB of memory region. Are they useful
> with your driver?
I'm not sure I follow, Toru. I'm talking about the TLB manager for an
Intel i860, the one on the PXG. It's there to swap pages between R3000 and
i860 address space (i.e. the 128/256kB SRAM on the card). It doesn't
really have to care where the pages come from in R3000 space, as long as
the Xserver is DTRT.
To add more mess to the whole thing, the PXG doesn't need packet buffers
in main memory. You have to have them on the SRAM, since that's all
the STIC sees on the PXG.