Here goes a short description of DECstation SCSI compiled last June 6th
as a personal communication for one of my friend.

[1] SII DC7061 based for DECstation 3100

SII was a custom SCSI controller designed by Digital. It was also used
with some of desktop/deskside VAX or DECsystem in that age. 

It had 128KB local SRAM as a scratch area.  All of data transfer between
main memory and SII must be done with bcopy()ing of scratch SRAM.

[2] NCR53C94 based for DECstation 5000/200

SCSI controller was replaced with off-the-shelf component.  It behaved
as a TURBOchannel device, but overall structure left untouch.  It had
128KB SRAM as SCSI scratch area.  PMAZ-AA was a standalone version.

[3] IOASIC DMA assisted NCR53C94 for IOASIC DECstations

DECstations finally got SCSI DMAing between its controller and its
main memory.  IOASIC has two special registers to hold the address of
transfering data.  These work like FIFO to allow interrupt machinary
to feed 'next' data address to be transfered in timely manner.  This
is the area in which ULTRIX could do and NetBSD/pmax can not. 

Mitchael Hitch made clear that PMAZ-AA is clocked by TC using an
electronical instrument.  He got a proof that IOASIC SCSI is driven
with 25MHz clock in spite of 3MIN and MAXINE have 12.5MHz (half of
3MAX and 3MAX+) TURBOchannel. 

[4] TCDS designed for TC Alpha

The first generation of Alpha box was effectively Alpha CPU equipped
3MAX+ or MAXINE.  Digital designed a custom DMA engine 'TCDS' to
relieve SCSI from 'serialization' enforced by IOASIC.  TCDS looks
similar to ESP found in early SparcStations.  PMAZB-A/PMAZC-A were
standalone TURBOchannel option cards.  High end TC Alpha had 40MHz
faster SCSI controller.

It's quite technologically interesting to know TC option cards can be
interchangable between different CPUs.  Geneous Digital engineers made
similar efforts to make off-the-shelf PCI cards friendy with PCI Alpha
box.

Tohru Nishimura, still feeling funny to see 'Q' displayed on Digitals
Nara Institute of Science and Technology