> I got the following error when I booted my /240:
>
>    cpu0 at mainbus0: MIPS R3000 CPU Rev. 3.0 with MIPS R3010 FPC Rev. 4.0
>            L1 cache: 64kb/0b Instruction, 64kb/0b Data. Direct mapped.
>            No L2 cache.
>    This kernel doesn't work without L2 cache.
>    Please add "options MIPS3_FLUSH"to the kernel config file.
>    halted.
>
> The R3000 is only a MIPS1 CPU, however the check for mips_L2CachePresent
> is in a section of code that is "#ifdef MIPS3", but not checking if we
> are on a MIPS3-type CPU.

The trouble above was an artifact of (forthcoming) NetBSD/arc integration.

> Whatever the correct solution is, I believe I should be able to build a
> GENERIC kernel and boot it on any machine...
>
>
> Also, should the cache line sizes not be printed out if they are not
> known?  I think

I revamped mips_machdep.c CPU parameter indetification logic with CPU
PRid table, and my MIPS1 only kernel now prints like;

	mainbus0 (root)
	cpu0 at mainbus0
	cpu0: MIPS R3000 CPU Rev. 3.0 with MIPS R3010 FPC Rev. 4.0
	cpu0: 64kb Instruction, 128kb Data, direct mapped cache
	tc0 at mainbus0: 12.5 MHz clock

Commit will happen in near feature.

Tohru Nishimura
Nara Institute of Science and Technology