On Wed, 3 Jun 1998 19:09:13 -0700 (PDT) 
 Jonathan Stone <jonathan@DSG.Stanford.EDU> wrote:

 > I haven't seen them, but I understand that the DEC drivers (both OSF/1
 > and Ultrix) set a slow 53c94 clock on half-speed TC busses.  The
 > Mach/SPrite code in 4.4BSD/pmax did so, too I think we should
 > understand why they did that, and be sure it's safe not to, before
 > changing.

I'll check again, but I'm 99.99% certain OSF/1 runs them at 25MHz.  The
chip's clock is provided by the card.  (Note, some TCDSs run at 40MHz on
25MHz TurboChannel busses...)

 > I'm guessing, but could it be poissble for 2 or 3fast-clocked 53c94
 > PMAZ-As to overrun a 12.5MHz TC bus (or the host memory system)
 > causing DMA overrun and data loss?

PMAZ-As do not even access host memory, so this wouldn't be a problem.  In
the TCDS example above, the timing difference is accounted for with a buffer
area on the card where the data is `staged'[*] (remember - you get one
interrupt per up-to-8k DMA segment on a TCDS, so this buffer doesn't even
have to be large).

[*] The TCDS can _almost_ be thought of as a pair of PMAZ-As and an
intermediary DMA engine that copies from the on-board ASC DMA buffer
to host RAM.  Almost.

 > So even if it works in practice, I'd be reluctant to commit this
 > unless it's sysctlable and defaults to off. Make sense?

Maybe patchable, but you don't add sysctls for drivers like that.  In any
case, like I said, since the PMAZ-A doesn't even traverse the TurboChannel
during a data transfer, the TurboChannel clock doens't even have to come
into play.

Jason R. Thorpe                                       thorpej@nas.nasa.gov
NASA Ames Research Center                            Home: +1 408 866 1912
NAS: M/S 258-5                                       Work: +1 650 604 0935
Moffett Field, CA 94035                             Pager: +1 650 428 6939