> In message <199805270424.VAA08150@lestat.nas.nasa.gov> Jason Thorpe writes:
> : Flushing the write buffer certainly is necessary... at least in the
> : Alpha architecture, the write buffer could be thought of as even
> : before the primary cache, since the chip may attempt write combining.
> 
> OK.  Things are a little different on the MIPS because uncached access
> to a memory location is uncached.  No write combination happens.  This
> is an observation, not something I recalled reading somewhere, so I'll
> defer to those with greater knowledge in this area if it turns out
> that I somehow got lucky.

I'm pretty sure the uncached, unmapped  space will NOT combine writes.  

On the R5K series (not sure about the R2K and R4K), at least, 
one can choose from a variety of behaviors for the cached, unmapped
space, ranging from providing only write buffering, to write-through,
and write back caching.

This can also be chosen on a per TLB basis.  Do any of the other
NetBSD architectures have anything similar implemented?