On Tue, 26 May 1998 22:27:56 -0600 
 Warner Losh <imp@village.org> wrote:

 > I recall from the R4400 that is in my Deskstation that I needed to do
 > all accesses to the mailbox of the buslogic card via uncached memory,
 > both reads and writes.  When I tried to do it via kernel memory I had
 > all kinds of cache coherency problems.  I don't think you need to
 > flush the write buffers when you do all your accesses uncached, but it
 > couldn't hurt.

Flushing the write buffer certainly is necessary... at least in the
Alpha architecture, the write buffer could be thought of as even
before the primary cache, since the chip may attempt write combining.

Jason R. Thorpe                                       thorpej@nas.nasa.gov
NASA Ames Research Center                            Home: +1 408 866 1912
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