On Thu, 23 Apr 1998, Michael L. Hitch wrote:

> On Apr 23,  2:33pm, David Evans wrote:
> >   From looking at code in mach_init() from mips/mips/machdep.c, it would appear
> > that only the first two TLB entries are ever touched--the rest are left in
> > their default state.  Should the PROM monitor normally be invalidating all of
> > the entries?
> 
>   Take a look at mips_vector_init() - it explicitly flushes the random TLB
> entries.
> 
>   By the time the kernel gets to starting /sbin/init, there should be quite
> a number of valid TLB entries.  All the kernel virtual memory is mapped
> using the TLB, and the kernel should have initialized lots of data by that
> point.

Speaking of TLB entries, there's something which is confusing me.  It looks
like 8 TLB entries are "wired down", i.e. not subject to random replacement,
in the R4000 code, but only the bottom three are actually used, from
reading through cpu_switch.

Am I missing something here?

	-castor