On Sat, 30 Aug 1997 01:24:23 -0700  Jonathan Stone wrote:

> Simon Burge <simonb@telstra.com.au> writes:
> 
> >Looking through the on-line R4000 user manual, I would guess that we'd
> >also need to set UX in the status register as well.  The only reference
> 
> Oops, Sorry, I took that as read.  Same with  FP regs, I think.

> Isn't there  an FPU bit to enable the 64-bit FP registers.

>From the same manual:

    Full 64-bit Operation.
        When the FR bit in the CPU Status register equals 0, the FPU
        is in 32-bit mode and contains thirty-two 32-bit registers
        that hold single- or, when used in pairs, double-precision
        values. When the FR bit in the CPU Status register equals 1,
        the FPU is in 64-bit mode and the registers are expanded to 64
        bits wide. Each register can hold single- or double-precision
        values. The FPU also includes a 32-bit Control/Status register
        that provides access to all IEEE-Standard exception handling
        capabilities.

> If so, I have no idea how to set it for binaries compiled with -mfp64
> that are otherwise mips1 binaries, Unless we use separate ECOFF or ELF
> code for those binaries, but I don't know off-hand of such codes.

Umm, easy :-)

vlad:~ 121> cc -mfp64 -c foo.c
cc1: Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers
vlad:~ 122> cc -mfp64 -mips3 -c foo.c
vlad:~ 123> 

Does anyone have experiance with 64-bit SGI systems?

Simon.