I concur with with the recollection about lack of a timer on the
receive side.  Back when I babysat vaxes, we'd put Able VMZs in the
780s and relegated the DZs to 750s, because the DZs needed more
interrupts and the UBA750 had lower latency (or was it just less
overhead to find the interrupting device?) than the UBA780.

Polling is one possibility but I think there really is a problem with
interrupt latency with the current pmax code; hence my references to
jamming code into the interrupt handler.

I've increased the clock rate to get more accurate timing of packet
traces.  A 5k/200 running NetBSD can get real work done at a ~ 2ms RTC
tick interval.  It never finishes booting at ~1 ms RTC tick interval.
Which leads me to conjecture that there's a real problem with
interrupt latency.

Doesn't the Zilog SCC have three chars worth of buffering?  Though I
agree serial DMA would be nice, specially for IP.  But surely the Mac
port has a respectable driver for the SCC by now? Couldn't we we just
take it and run?


anyway I *am* having fun but wish there was more time for sleep,
--Jonathan