Well, the DS3100 functional spec. lists 19,800bps (not 19.2) as the only
speed higher that 9600 supported by the DC7085. It also notes that the 4
ports share a 64byte receive silo, so I think the problem is the weird
hardware clock and not receive interrupt latency. (My vague recollection
is that the hassle with the DZ is that it doesn't have a timer on the receive
silo, so you either have to live with an interrupt on every character or
probe the receive side from a timeout(). For old vaxen (I once ran a 780 with
64 DZ ports:-), the DZs generated so many interrupts that you needed the hand
coded assembler to save those precious cycles and, as someone else noted, this
shouldn't be so critical for the DS3100.

I can't remember how many receive chars get buffered in the scc chip, but I
never did figure out how to avoid large interrupt latencies, so I would be
concerned about getting it to work well (the driver I hacked from the Mach3.0
one never did:-). I remember thinking about how you might be able to use the
dma capabilities and then monitor progress through the dma buffer from a
timeout(), but never tried it.

Have fun, rick