> 
> Bizzare. I'm surprised MIPS didn't put a specific flush mechanism into
> the processor (a pipeline stall is cheaper than a loop checking for
> completion.)
> 
Designers fredom of choise! :). R2000/R3000 dont have on chip write queues.
And you dont have to have them at all (eg in embedded systems with fast sram
only). Another problem similar to this is multiprocessor synchronization...
R4[0246]00's is somewhat more complex. Although it has a 'SYNC' instruction.

> Yeah. The book I have says that IDT processors work in the following
> way: If a read is done from an uncached address, the processor stalls
> until the write buffer has flushed. (Apparently to make flushing easy,
> and so that they didn't need write-then-read collision detection
> circuitry.)
> 
Yes, The 79R30[4578]1 have a four word write pipeline onboard. Writes
has priority and reads to uncached space and cache misses have to wait.

Per