Re: Got further, am stuck now, here's a patch

[coypu%SDF.ORG@localhost]

Also forgot this part.
GCC complains about the use of dmfc0/dmtc0.
In the absence of documentation, who knows, but this is necessary to
get further in building.

Index: arch/mips/mips/locore_mips3.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/locore_mips3.S,v
retrieving revision 1.112
diff -u -p -r1.112 locore_mips3.S
--- arch/mips/mips/locore_mips3.S	11 Jul 2016 16:15:36 -0000	1.112
+++ arch/mips/mips/locore_mips3.S	19 Jul 2016 13:46:11 -0000
@@ -699,7 +699,7 @@ END(baderr64)
  * and ASID bits are implemented.  Assumes that interrupts are disabled.
  */
 LEAF(mips3_cp0_tlb_entry_hi_probe)
-	dmfc0	t0, MIPS_COP_0_TLB_HI
+	_MFC0	t0, MIPS_COP_0_TLB_HI
 	li	v0, -1		/* all 1s */
 #if defined(__mips_isa_rev) && __mips_isa_rev >= 2
 	dinsu	v0, zero, 62, 2
@@ -707,10 +707,10 @@ LEAF(mips3_cp0_tlb_entry_hi_probe)
 	dsll	v0, v0, 2	/* except the top 2 */
 	dsrl	v0, v0, 2
 #endif
-	dmtc0	v0, MIPS_COP_0_TLB_HI
+	_MTC0	v0, MIPS_COP_0_TLB_HI
 	COP0_SYNC
-	dmfc0	v0, MIPS_COP_0_TLB_HI
-	dmtc0	t0, MIPS_COP_0_TLB_HI
+	_MFC0	v0, MIPS_COP_0_TLB_HI
+	_MTC0	t0, MIPS_COP_0_TLB_HI
 	COP0_SYNC
 	nop
 #ifdef __mips_o32
@@ -736,12 +736,12 @@ END(mips3_cp0_tlb_entry_hi_probe)
  * PA bits are implemented.  Assumes that interrupts are disabled.
  */
 LEAF(mips3_cp0_tlb_entry_lo_probe)
-	dmfc0	t0, MIPS_COP_0_TLB_LO0
+	_MFC0	t0, MIPS_COP_0_TLB_LO0
 	li	v0, -64		/* all 1s except low 6 bits */
-	dmtc0	v0, MIPS_COP_0_TLB_LO0
+	_MTC0	v0, MIPS_COP_0_TLB_LO0
 	COP0_SYNC
-	dmfc0	v0, MIPS_COP_0_TLB_LO0
-	dmtc0	t0, MIPS_COP_0_TLB_LO0
+	_MFC0	v0, MIPS_COP_0_TLB_LO0
+	_MTC0	t0, MIPS_COP_0_TLB_LO0
 	COP0_SYNC
 #ifdef __mips_o32
 #if BYTE_ORDER == BIG_ENDIAN