Frank Wille says;

> While reading the doc, I found other interesting facts.
>
> 1. We don't need to clear the interrupt pin register (0x3d) of the IDE
>   controller. This is a read-only register, which is 0 in legacy mode and 1
>   in native mode.

I suspect the VIA documents do not always mention realities.  In all
586/686/8231 PDFs, IDE 0x3d pin designation is consistently noted RO,
however, I can change the byte in 686SB to tell NetBSD logic to switch
compat or PCI native.  Note that 1 means 'pin A' and given deep doubt
of the technical possiblity to make the IDE route PCI interrupt out of it,
pin A designation would make little sense, I believe.

Toru Nishimura/ALKYL Technology