Algorithmics P4000: Technical Documentation, Memory Map, and RAM Controller Details

[DiTBho Down in The Bunny hole <downinthebunnyhole%gmail.com@localhost>]

Hi everyone,
I hope this email finds you well.

As part of a retrocomputing and educational hardware preservation
project, I am currently working on resurrecting an Algorithmics P4000
MIPS evaluation board (from around 1994, featuring the 72-pin SIMM
sockets, a SONIC Ethernet controller, an ST Timekeeper RTC, and an IDT
chipset).

Since complete and structured documentation online is quite scarce, I
was wondering if anyone in the community might have (or know where to
find) a digital, scanned, or transcribed copy of the P-4000 User's
Manual or related hardware specs.

Specifically, I am looking for information regarding:

Maximum Addressable Memory & EDO Support: What is the hard limit for
the onboard SIMM slots? Has anyone ever successfully run EDO RAM on
this board, or is it strictly limited to Fast Page Mode (FPM) DRAM?

RAM Controller Jumpers: Are there any undocumented or documented
jumpers or configuration pins on the board/RAM controller (e.g., to
handle interleaving or tweak memory timings)?

Complete Memory Mapping: A breakdown or summary of the physical
address map for the board's main devices, including:

Main DRAM mapping (and uncached/cached segments)
+ ROM / Boot EPROM space
+ Serial ports registers
+ Ethernet controller (SONIC)
+ RTC / NVRAM (MK48T02B Timekeeper)

Any hints, pointers, or old notes you might be willing to share would
be hugely appreciated to help bring this board back to life.

Thank you very much for your time and expertise!

Best regards,
D.