Re: Crazy cross-MIPS-boards stunts possible?

["Maciej W. Rozycki" <macro%linux-mips.org@localhost>]

On Wed, 2 Dec 2020, Jonathan Stone wrote:

> Mips r2000 and r3000 devices were bi-endian, but endianess was chosen
> globally at reset.

 Some later MIPS I implementations had the reverse-endian mode too 
according to my sources, starting with the R3000A.

> If dimming memory serves, R4000 (MIPS-III?) could set endian-ness per 
> process, and would change to "system endian-ness (reset-time 
> endian-ness) when changing from user to kernel mode.

 The bootstrap aka kernel-mode endianness was strapped at reset; with the 
R4000 and many later designs preset with a boot mode bit, which in some 
system designs could be controlled indirectly via software (e.g. the 
Algorithmics' Bonito system controller could be asked by software to reset 
the CPU with a modified boot mode bit stream; this was a way to adjust the 
number of TLB entries with the QED RM7000 series CPUs for example).

 The endianness for the user mode could have been overridden, perhaps on a 
per-task basis, with the Reverse-Endian bit in the CP0 Status register.  
It has been architecturally supported ever since the introduction of the 
modern embedded MIPS ISA and many implementations supported it as it was 
easy to do, however I have yet to hear of actual use.

> The kernel would need to keep track of process (address space) 
> endian-ness. Byte-swapping of syscall parameters, etc. would be 
> necessary. That's as far as I got, 20-odd years ago, when looking into 
> supporting mipseb on r4k mipsel (or vice-versa). Doable, in principle, 
> but it's never been a priority for anyone.

 The toughest part has been byte-swapping structure members when passing 
them between the kernel and the userland.  The complication around it made 
everyone I know of who has tried to give up.  It would be much easier with 
virtualisation nowadays though, which I'm told tends to use network-like 
packet protocols to communicate between the host and the guests.  I don't 
know what the status of this is with the MIPS architecture, and given the 
state of affairs with the MIPS world whatever has not materialised so far 
may well never happen.

 FWIW,

  Maciej