Re: COP0_SYNC definition

[Michael <macallan%netbsd.org@localhost>]

Hello,

On Sat, 18 Jun 2016 13:35:28 +0000
coypu%SDF.ORG@localhost wrote:

> We define in sys/arch/mips/include/cpuregs.h:157
> #  define JR_HB_RA              .set push; .set mips32r2; jr.hb ra; nop;
> 
> for case of MIPSnnR2 only.
> 
> I think that either this nop is superfluous, or it should be ehb/ssnop.
> I can't imagine a new implementation will ever require just a simple nop
> as padding, aren't they all likely superscalar?

I tried to find out if xburst is - couldn't find any halfway decent
docs on the CPU itself other than "it's mips32r2, there's a SIMD
extension we don't give you docs for either, now bugger off!". Speed is
more or less comparable to a Cortex A7 at the same clock, so it
probably is. There's not a word about CP0 hazards in the jz4780 manual.

Loongson 2 and newer certainly are, they proudly advertised that. The
2F manual says "The processor detects most of the pipeline hazards in
hardware, including CP0 hazards and load hazards. No NOP instructions
are required to correct instruction sequences."
So lumping them together with old MIPS-III at least does no harm.

have fun
Michael