MIPS 74K and execution hazards

["Gregory T. Andersen" <gandersen%cradlepoint.com@localhost>]

Has anyone done any work for MIPS 74K CPUs (mips32r2)?  We have run into 
an issue where it seems a lot of the low level code (mipsX_subr.S, 
locore.S) does not have support for MIPS execution hazards.  The big 
offenders seem to be the TLB/CP0 instructions (tlbp, tlbw, mtc0, mfc0, 
etc..).

Rather than use nop slots after instructions MIPS32 requires use of 
ssnop (mips32r1) or ehb (mips32r2) instructions to guarantee clearing of 
execution hazards in MIPS superscaler designs.

We have a heavy handed solution in place to get the kernel booting but 
were curious if anyone had implemented a more elegant/tested solution?

Greg Andersen
Cradlepoint Technology