Subject: Re: port-mips/31915: provide centralized wired_map logic
To: Garrett D'Amore <garrett_damore@tadpole.com>
From: Garrett D'Amore <garrett_damore@tadpole.com>
List: port-mips
Date: 10/27/2005 13:11:16
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Attached find my updates. These conditionalize the inclusion of the
wired map logic, and they allow for slightly more granular entries (16MB
pages instead of 32 MB entries.)
I'm not attaching the files that I have not changed since my first set
of diffs.
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Index: sys/arch/mips/conf/files.mips
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/conf/files.mips,v
retrieving revision 1.1.1.1
retrieving revision 1.5
diff -c -r1.1.1.1 -r1.5
*** sys/arch/mips/conf/files.mips 29 Sep 2005 16:42:46 -0000 1.1.1.1
--- sys/arch/mips/conf/files.mips 27 Oct 2005 20:05:33 -0000 1.5
***************
*** 13,18 ****
--- 13,19 ----
# ENABLE_MIPS_R3NKK
defflag opt_mips_cache.h MIPS3_NO_PV_UNCACHED
ENABLE_MIPS4_CACHE_R10K
+ defflag opt_mips3_wired.h ENABLE_MIPS3_WIRED_MAP
file arch/mips/mips/locore_mips1.S mips1
file arch/mips/mips/locore_mips3.S mips3 | mips4 | mips32 | mips64
***************
*** 37,42 ****
--- 38,44 ----
file arch/mips/mips/vm_machdep.c
file arch/mips/mips/process_machdep.c
file arch/mips/mips/cpu_exec.c
+ file arch/mips/mips/mips3_wired_map.c enable_mips3_wired_map & !mips1
file arch/mips/mips/cache.c
file arch/mips/mips/cache_r3k.c mips1
Index: sys/arch/mips/mips/mipsX_subr.S
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/mips/mipsX_subr.S,v
retrieving revision 1.1.1.1
retrieving revision 1.3
diff -c -r1.1.1.1 -r1.3
*** sys/arch/mips/mips/mipsX_subr.S 29 Sep 2005 16:42:52 -0000 1.1.1.1
--- sys/arch/mips/mips/mipsX_subr.S 27 Oct 2005 20:05:34 -0000 1.3
***************
*** 118,123 ****
--- 118,124 ----
#include "opt_cputype.h"
#include "opt_ddb.h"
#include "opt_kgdb.h"
+ #include "opt_mips3_wired.h"
#include <sys/cdefs.h>
***************
*** 1593,1598 ****
--- 1594,1652 ----
nop
END(MIPSX(SetPID))
+ #if defined(ENABLE_MIPS3_WIRED_MAP)
+ /*--------------------------------------------------------------------------
+ *
+ * mipsN_TLBWriteIndexedVPS --
+ *
+ * Write the given entry into the TLB at the given index.
+ * Pass full r4000 tlb info including variable page size mask.
+ *
+ * mipsN_TLBWriteIndexed(index, tlb)
+ * unsigned index;
+ * tlb *tlb;
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * TLB entry set.
+ *
+ *--------------------------------------------------------------------------
+ */
+ LEAF(MIPSX(TLBWriteIndexedVPS))
+ _MFC0 v1, MIPS_COP_0_STATUS # Save the status register.
+ _MTC0 zero, MIPS_COP_0_STATUS # Disable interrupts
+ nop
+ lw a2, 8(a1)
+ lw a3, 12(a1)
+ _MFC0 v0, MIPS_COP_0_TLB_PG_MASK # Save current page mask.
+ _MFC0 t0, MIPS_COP_0_TLB_HI # Save the current PID.
+
+ _MTC0 a2, MIPS_COP_0_TLB_LO0 # Set up entry low0.
+ _MTC0 a3, MIPS_COP_0_TLB_LO1 # Set up entry low1.
+ nop
+ lw a2, 0(a1)
+ lw a3, 4(a1)
+ nop
+ _MTC0 a0, MIPS_COP_0_TLB_INDEX # Set the index.
+ _MTC0 a2, MIPS_COP_0_TLB_PG_MASK # Set up entry mask.
+ _MTC0 a3, MIPS_COP_0_TLB_HI # Set up entry high.
+ nop
+ tlbwi # Write the TLB
+ nop
+ nop
+ nop # Delay for effect
+ nop
+
+ _MTC0 t0, MIPS_COP_0_TLB_HI # Restore the PID.
+ nop
+ _MTC0 v0, MIPS_COP_0_TLB_PG_MASK # Restore page mask.
+ j ra
+ _MTC0 v1, MIPS_COP_0_STATUS # Restore the status register
+ END(MIPSX(TLBWriteIndexedVPS))
+ #endif /* ENABLE_MIPS3_WIRED_MAP */
+
/*--------------------------------------------------------------------------
*
* mipsN_TLBUpdate --
Index: sys/arch/mips/mips/mips3_wired_map.c
===================================================================
RCS file: sys/arch/mips/mips/mips3_wired_map.c
diff -N sys/arch/mips/mips/mips3_wired_map.c
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- sys/arch/mips/mips/mips3_wired_map.c 27 Oct 2005 20:05:34 -0000 1.2
***************
*** 0 ****
--- 1,176 ----
+ /* $NetBSD: wired_map.c,v 1.8 2005/01/22 07:35:33 tsutsui Exp $ */
+
+ /*-
+ * Copyright (c) 2005 Tadpole Computer Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Tadpole Computer Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Tadpole Computer Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+ /*
+ * Copyright (C) 2000 Shuichiro URATA. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*
+ * This code is derived from similiar code in the ARC port of NetBSD, but
+ * it now bears little resemblence to it owing to quite different needs
+ * from the mapping logic.
+ */
+
+ #include <sys/cdefs.h>
+ __KERNEL_RCSID(0, "$NetBSD$");
+
+ #include <sys/param.h>
+ #include <sys/systm.h>
+ #include <uvm/uvm_extern.h>
+ #include <machine/cpu.h>
+ #include <machine/locore.h>
+ #include <machine/pte.h>
+ #include <mips/wired_map.h>
+
+ static struct wired_map_entry {
+ paddr_t pa0;
+ paddr_t pa1;
+ vaddr_t va;
+ } wired_map[MIPS3_WIRED_ENTRIES];
+
+ static boolean_t mips3_wire_down_page(vaddr_t va, paddr_t pa);
+ static int nwired;
+
+ boolean_t
+ mips3_wire_down_page(vaddr_t va, paddr_t pa)
+ {
+ struct tlb tlb;
+ int index;
+ int found = 0;
+
+ if ((va & MIPS3_WIRED_OFFMASK) || (pa & MIPS3_WIRED_OFFMASK))
+ panic("mips3_wire_down_page: not aligned");
+
+ for (index = 0; index < nwired; index++) {
+ /* search low and high... */
+ if (wired_map[index].va == va) {
+ wired_map[index].pa0 = pa;
+ found++;
+ break;
+ }
+ if ((wired_map[index].va + MIPS3_WIRED_SIZE) == va) {
+ wired_map[index].pa1 = pa;
+ found++;
+ break;
+ }
+ }
+ if (found == 0) {
+ /* we have to allocate a new wired entry */
+ if (nwired >= MIPS3_WIRED_ENTRIES)
+ return 0;
+ index = nwired;
+ nwired++;
+ wired_map[index].va = va;
+ wired_map[index].pa0 = pa;
+
+ /* Allocate new wired entry */
+ mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES + nwired + 1);
+ }
+
+ /* map it */
+ tlb.tlb_mask = MIPS3_WIRED_PG_MASK;
+ tlb.tlb_hi = mips3_vad_to_vpn(va);
+ if (wired_map[index].pa0 == 0)
+ tlb.tlb_lo0 = MIPS3_PG_G;
+ else
+ tlb.tlb_lo0 = mips3_paddr_to_tlbpfn(wired_map[index].pa0) |
+ MIPS3_PG_IOPAGE(PMAP_CCA_FOR_PA(wired_map[index].pa0));
+ if (wired_map[index].pa1 == 0)
+ tlb.tlb_lo1 = MIPS3_PG_G;
+ else
+ tlb.tlb_lo1 = mips3_paddr_to_tlbpfn(wired_map[index].pa1) |
+ MIPS3_PG_IOPAGE(PMAP_CCA_FOR_PA(wired_map[index].pa1));
+ MachTLBWriteIndexedVPS(MIPS3_TLB_WIRED_UPAGES + index, &tlb);
+ return 1;
+ }
+
+
+ /*
+ * Wire down pages. Returns the actual size wired down, as we may
+ * have to wire down more memory than that. In general, we always
+ * wire down 16 MB at a time, to simplify the logic.
+ *
+ * Typically the caller will just pass a physaddr that is the same as
+ * the vaddr with bits 35-32 set nonzero.
+ */
+ boolean_t
+ mips3_wire_down(vaddr_t va, paddr_t pa, vsize_t size)
+ {
+ vaddr_t vend;
+ /*
+ * This routine allows for for wired mappings to be set up,
+ * and handles previously defined mappings and mapping
+ * overlaps reasonably well. However, caution should be used
+ * not to attempt to change the mapping for a page unless you
+ * are certain that you are the only user of the virtual
+ * address space, otherwise chaos may ensue.
+ */
+
+ /* offsets within the page have to be identical */
+ if ((va & MIPS3_WIRED_OFFMASK) != (pa & MIPS3_WIRED_OFFMASK))
+ panic("mips3_wire_down: mismatched offsets!");
+
+ vend = va + size;
+ /* adjust for alignment */
+ va &= ~MIPS3_WIRED_ENTRY_OFFMASK;
+ pa &= ~MIPS3_WIRED_ENTRY_OFFMASK;
+
+ while (va < vend) {
+ if (!mips3_wire_down_page(va, pa))
+ return 0;
+ va += MIPS3_WIRED_ENTRY_SIZE;
+ pa += MIPS3_WIRED_ENTRY_SIZE;
+ }
+ return 1;
+ }
Index: sys/arch/mips/include/wired_map.h
===================================================================
RCS file: sys/arch/mips/include/wired_map.h
diff -N sys/arch/mips/include/wired_map.h
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- sys/arch/mips/include/wired_map.h 27 Oct 2005 20:09:39 -0000
***************
*** 0 ****
--- 1,86 ----
+ /* $NetBSD: wired_map.h,v 1.2 2005/01/22 07:35:33 tsutsui Exp $ */
+
+ /*-
+ * Copyright (c) 2005 Tadpole Computer Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Tadpole Computer Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Tadpole Computer Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ #ifndef _MIPS_WIRED_MAP_H
+ #define _MIPS_WIRED_MAP_H
+
+ /*
+ * Certain machines have peripheral busses which are only accessible
+ * using the TLB.
+ *
+ * For example, certain Alchemy parts place PCI and PCMCIA busses at
+ * physical address spaces which are beyond the normal 32-bit range.
+ * In order to access these spaces TLB entries mapping 36-bit physical
+ * addresses to 32-bit logical addresses must be used.
+ *
+ * Note that all wired mappings are must be 32 MB aligned. This is
+ * because we use 32 MB mappings in the TLB. Changing this might get
+ * us more effficent use of the address space, but it would greatly
+ * complicate the code, and would also probably consume additional TLB
+ * entries.
+ *
+ * Note that within a single 32 MB region, you can have multiple
+ * decoders, but they must decode uniquely within the same 32MB of
+ * physical address space.
+ *
+ * BEWARE: The start of KSEG2 (0xC0000000) is used by the NetBSD kernel
+ * for context switching and is associated with wired entry 0. So you
+ * cannot use that, as I discovered the hard way.
+ *
+ * Note also that at the moment this is not supported on the MIPS-I
+ * ISA (but it shouldn't need it anyway.)
+ */
+ #define MIPS3_WIRED_PG_MASK MIPS3_PG_SIZE_16M /* 16 MB */
+ #define MIPS3_WIRED_SIZE MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_WIRED_PG_MASK)
+ #define MIPS3_WIRED_OFFMASK (MIPS3_WIRED_SIZE - 1)
+
+ /*
+ * This defines the maximum number of wired TLB entries that the wired
+ * map will be allowed to consume. It can (and probably will!)
+ * consume fewer, but it will not consume more. Note that NetBSD also
+ * uses one wired entry for context switching (see TLB_WIRED_UPAGES),
+ * and that is not included in this number.
+ */
+ #ifndef MIPS3_WIRED_ENTRIES
+ #define MIPS3_WIRED_ENTRIES 8 /* upper limit */
+ #endif /* MIPS3_WIRED_ENTRIES */
+
+
+ /*
+ * Wire down a mapping from a virtual to physical address. Note that
+ * the size of the region must be a multiple of 32 MB (WIRED_ENTRY_SIZE)
+ * and the alignment must be on a 32 MB (WIRED_ENTRY_SIZE) boundary.
+ */
+ boolean_t mips3_wire_down(vaddr_t, paddr_t, vsize_t);
+
+ #endif /* _MIPS_WIRED_MAP_H */
--------------050107090600000603080004--