M. Warner Losh wrote:

>In message: <20050930183324.GA28951@NetBSD.org>
>            Andrey Petrov <petrov@NetBSD.org> writes:
>: On Fri, Sep 30, 2005 at 09:08:07AM -0700, Garrett D'Amore wrote:
>: > Thanks for the advice.  It looks like I need to change the size of 
>: > paddr_t, to accomodate a larger 36-bit value.  (The ARC port already 
>: > does this, though I don't know why it needs 64-bit values here.)
>: > 
>: 
>: If you need 36-bit address (constant prefixes even) only for PCI access then
>: likely you can work it out in your bus_.. functions. And that wouldn't justify
>: larger paddr_t and new port, I understand temptation thou -)
>
>You still need to map those addresses into a 32-bit address space
>somehow.  You may need to do something special in the bus* functions
>as well, but the basic mapping has to be there first.  Since PCI bus
>acccesses are likely to be common, it likely makes good sense to
>hard-wire a page of appropriate size to cover the PCI bus in the TLB.
>  
>
Yes.  And hence I've decided to create an aumips port that has a 
different paddr_t (it will be 64 bit).  I'm planning on borrowing as 
much of the logic for wiring this external space from the ARC port as I can.

I figure a single 16MB page for PCI configuration space, and then 
allocate the rest "on demand" as PCI functions need their addresses 
mapped.  I'll do it in 16MB chunks with the hope of reducing the number 
of mappings.  However, the framebuffer we are using is going to need a 
32MB chunk, so we're looking to see at least 4 of these 16MB pages wired.

I expect I'll have this worked out next week sometime.  Hopefully I'll 
eventually be submitting a patch to add this support for the alchemy parts.

    -- Garrett

>Warner
>  
>