Thanks for the advice.  It looks like I need to change the size of 
paddr_t, to accomodate a larger 36-bit value.  (The ARC port already 
does this, though I don't know why it needs 64-bit values here.)

I believe this means I have to create a new port, so that I can provide 
my own types.h to override the size of the paddr_t, just like the ARC 
port does.  I'm proposing that this port be called "aumips".

Does anyone have any advice about the wisdom of this course of action?  
Any suggestions for better courses?

    -- Garrett

Andrey Petrov wrote:

>On Thu, Sep 29, 2005 at 08:53:56PM -0700, Garrett D'Amore wrote:
>  
>
>>Alex Pelts wrote:
>>
>>    
>>
>>>Hmm,
>>>I have no experience with that particular board but as far as I know 
>>>most mips systems have 32 bit address bus. What mips core is on that 
>>>board?
>>>If this is alchemy core it is only 14 bit address bus, so I can't see 
>>>how you can address 36bit address space. It also looks like 32 bit 
>>>mips which makes it questionable about 36 bit access as well.
>>>      
>>>
>>It is an Amd/Alchemy Au1550 core.
>>
>>    
>>
>>>I may be wrong here but I think you are mistaking about 36 bit address 
>>>space.
>>>      
>>>
>>No, I'm fairly certain about this.
>>
>>The core is an Au1 core, and while the processor is indeed a MIPS32 
>>based core, it has what it calls a 36-bit system bus.  The upper 4 bits 
>>are mapped to various chip selects for peripherial busses.
>>
>>For example PCI address look this:
>>
>>0x0140050xx - Au1550 configuration registers
>>0x0140051xx - Au1550 PCI header space
>>0x4xxxxxxxx - PCI memory space
>>0x5xxxxxxxx - PCI I/O space
>>0x6xxxxxxxx - PCI external configuration space
>>
>>So you set those top 4 bits (bits 33-35) to indicate use of the PCI bus 
>>and the type of PCI access to use (memory, IO, or configuration).  (The 
>>other addresses at 14005xxx are for accessing the Au1550's own PCI 
>>configuration and for configuring things like PCI host operation.
>>
>>The manual is also pretty clear in stating that the only way to get at 
>>this area of address space is thru the TLB, using a 32-bit virtual 
>>address to map to a 36-bit physical address.
>>
>>I guess what I need to do is set up some kind of fixed TLB entries for 
>>this.  Any guidance in how to do *that* would be appreciated.
>>
>>As far as I can tell, these addresses are really only necessary for PCI, 
>>but I've not checked every inch of the 200+ page datasheet for any other 
>>references to "high" (above 4GB) memory.
>>
>>    
>>
>
>Access to devices is handled by bus_space(9) and bus_dma(9) so I'd start from
>there.
>
>Andrey
>  
>