Here goes an excerpt from IDT R30xx software reference manual.
It has been rewritten many times to adapt later IDT products.  I think
this old one is most valuable...

---
Context Convenience register provided to speed up the processing
of TLB refill traps. The high-order bits are read/write; the
low-order 21 bits reflect the BadVaddr value.
(The register is designed so that, if the system uses the
''favored'' arrangement of memory-held copies of memory
translation records, it will be setup by a TLB refill trap to
point to the memory location of the record needed to map
the offending address. This speeds up the process of
finding the current memory mapping, and arranging
EntryHi/Lo properly).
---

It's somehow fun to know that the doc does not mention to what 
favoured arrangement' really is...

The single PDF I found so far which makes clear context register
definition is Aurora VLSI.

Toru Nishimura/ALKYL Technology