(cgd tossed a coin)

People who own  Dominic Sweetman book and Vahalia book
have already understoodd MIPS ASID magic and VPT (DEC term),
aka, linear PTE mapped in KSEG2 virtual address.  Now I would
like to point here that PTEbase register has not been discussed
in detail so far.  Few literature discloses the bit definition.  Some
are vague at best.

PTEbase is an convenience register to make short TLB refilling
exception handler.  Originally invented for R3000 processor, TLB
refill exception is expected done just for user space VM activity.
The decision is a mystery for me why KSEG2 TLB miss was not
a part of R3000 TLB refill.  They named it "UTLB miss"

http://www.alkyltechnology.com/files/MIPScontextreg.pdf

R3000 PTEbase register is made of two portions.  PTE base
field bit[31:21] contains where linear PTE origin is.  bit[20:2]
comes from badvaddr VA[30:12].  The least significant 2 bits
are hardwired zero.  This arrangement requires 2MB linear
PTE range to cover 2GB user VA range.  KSEG2 TLB miss
is out of sight.

The R4000 designer changed their mind.  They realized
KSEG2 TLB miss should have been a part of fast TLB refill
exception control path.  They put a new name "TLB refill".
The new context definition makes it clear that their intent.
They are so 64bit-head while keeping minimal the 32->64
software transition burden.  HOWEVER, I think it's rather
their sin they made no good explanation behind the change.

Toru Nishimrua/ALKYL Technology