VCE can happen with R4000/4400 SC/MC models.  Many seem
confused by the intent.  Some literatures mention it's useful to solve
virtual alias condition, with a few insns at worst.  However, as virtual
alias does matter for all VIPT cache, VCE is just a half of solution
which makes sense for SC/MC models.  (Please consult PDF which
shows SC/MC L2 cache tag.  It contains VA[14:12] to detect virtual
alias condition.)

So, the Q is why VCE was invented and what's the real purpose
and condition which it tries to solve.  It's my 2nd puzzle about R4000
(the 1st is supervisor mode.  I don't believe Dominic explaination).

My guess is the R4000 designer wanted to allow cache line
variations across L1 and L2.  Modern (late '90 and 21st) processors
have single fixed cache lines common to L1 and L2.  R4000 is not
that case.

Now reader have realized NetBSD/mips runs a single lung and
CPU cycle is wasted for excess cache invalidations to avoid virtual
alias.  The reason is clear; VM is not aware of  "VA indexing" constraint.

Toru Nishimura/ALKYL Technology