> Today I've checked how much VCED happens on my R4400
> news5000 by disabling VCED/VCEI handlers in mipsX_subr.S.
> Well, it causes awful result. VCED happens right after
> init is started, so I'm suprised how R4600/R5000 machines
> (which don't have VCE hardware) are wokring on current kernels.

It's an accident which looks working.

> Other VCEDs occur mostly on pool, because current mips pmap
> use KSEG0 address for pool pages (which is defined in pmap.h):

Truth is like this.  R3000 was a plain good 32bit processor.  It has
PITA/write-thru cache and its line size was quite small.  All these features
bring quite comfortable consequence; Near zero cache concern is
required for kernel programmer.   Only single case would matter.  Just
for DDB single stepping.  Icache must be forced synch. with Dcache right
after a BREAK instruction replaces the target insn.  MIPS has
software controlled single step debugging strategy and caches are
not unified (nor "forwarded" D->I).

When R4000 made a bold step forward to the complete new era of
microprocessor history in 1991, the technological gap was so huge.
Most of R3000 fanatic could not understand how OS must be
re-designed.

- VIPT cache.
It's known best cache machinary for UNIX style process model OS.
It, however, would bring virtual alias issue IF kernel programmer does
not pay attention to keep it from happening.  VM must be careful about
VA/PA binding to make no virtual alias. 
- write-back cache.
PIPT write-thru cache is transparent, i.e., little need to concern about the
existence, in most cases.  Write-back cache brings potentials in which
cache contents and memory disagree each other in any moment.   Bus
snooping by memory controller is the way to monitor and resolve by
shooting cache lines.   Until very recent bus snooping has not been
popular engineering feature in microprocessor market.   So, with
every effort and sweat complicated bus_dma(9) must be done to make
sure device drivers work correctly.   It's the best technological feature on
this planet and NetBSD can be proudful about the invention.  I believe
that PC-ranked kish eaters are not capable of understanding why
bus_dma(9) is required.

Au1 can do bus-snoop.  The VIPT cache is 16KB/4ways which means
it behaves PIPT cache in fact.  So Au1 could be called the revive of
R3000's PIPT/write-thru virtue.  So g'd bye virtual alias. 

Toru Nishimura/ALKYL Technology