Guys, who are concerning about MIPS cache issues,

I've been keeping a distance from NetBSD/mips cache/pmap
issue for long time.  The reason is few really understands
how R4000 VIPT cache works and how pmap should handle
them.  Please, in my sincere, make a research about the
reasoning and design consequence behind VIPT cache
BEFORE touching pmap.c code.   The last night I was
finally succesful to make Tsutsui-san enlightened about it.
(He had wrong idea about VIPT.  Not a personal offence,
you know).  Curt's cache/SMP book is the authority.

And if you are a person who is responsible to choose right
MIPS processor to go, I recommend you PMC-Sierra
RM7xxx/9xxx and/or AMD/Achemy Au1x00.  They are immune
from VIPT issue which wrecked NetBSD/mips badly.

Toru Nishimura/ALKYL Technology