Regarding to address space management, rumbling talk.

The 32bit address space arrangement was quite a plain decision
at the technology level of mid 1980 computer industry.   The
simplicity of R3000 architecture is striking like Japanese gardens
or bonsai plants.  I can see no fril with it.   "I love R3000A"
Soon TLB design was changed for R6000.  TLBlo had paddr field
shifted toward MSB.  This was done because bit0-11field was under-
untilized and the arrange made possible to extend paddr beyond
32bit.  R6000 was proven a technonogical failure.  Then R4000 was
designed expecting it would be a jump start of server processor.
The 64bit design was a clear win.  It was done without bringing messy
complexity (AMD64 proved Itanium is wrong approach).  Address
space was carefully extended keeping in mind of 32bit layout compatibility.
The introduction of "supervisor mode" was a mystery.   Someone will disclose
the (real) story behind it.  R4000 TLB entry design is peculiar.  One can
handle doubled pagesize with dual PTEs at once.   R4000 TLB manipulates
vaddr in 8KB chunk while the halves can map two independent 4KB memory.
The strange arrangement keeps fine memory utilization whilst enlarges
manageable TLB vaddr range to twice larger without doubling costly
full-associative circuit.

There is a good retrospective summary by Tom Riordan, a MIPS guru, at
http://www.mips.com/content/PressRoom/TechLibrary/WhitePapers/files/64-bit_MIPS_Processors.pdf

Observing technological and economic realities of year 2004, RM7x35/7x65
or any choice of TX49 looks a preferable choice for me.

Toru Nishimura/ALKYL Technology