> TLB shootdown logic must be completed before SMP is realized.  It's
> done by IPI (Inter-Processor-Interrupt). 

IPI is a rather general form to notify "foreign processor" to do something.
Other SMP capable NetBSD ports, i386 and sparc* do have it.
ARCS specification includes IPI definition, and it'll be used to implement
TLB shootdown logic.  Unfortunately ARCS implementations in wide
variety of so-called NT boxes are known somehow inconsistent and there
is a kind of concern around how useful ARCS IPI really is.
Another camp of SMP MIPS hardware is apparently SGI.  I have little clue
about their implementation.  There are on-die multiprocessor hardware in
market.  SMP is "must" to facilitate the potentials.

Toru Nishimura/ALKYL Technology