Hi,

After I committed softintr(9) code for arc
I checked some related entries in arc/TODO file,
but I can't see whether some of them are solved or not.
(sorry, I'm not a mips guy)

>> -   if (ipending & INT_MASK_REAL_DEV) == 0,
>>     softnet() and softclock() are handled with all interrupt disabled.
>>         -> overblocking, possibly causes missing hardclock()

I guess calling _clrsoftintr() before calling softintr_dispatch()
solves this. Is it correct?

>> -   `netisr' handling in netintr() implies potential race condition.
>>     The access to `netisr' should be protected by splnet().
>>     Currently this is not real problem due to above overblocking.

I think current arch/mips/mips/trap.c:netintr() still has
this problem, but I wonder what is the right solution.
Should we add splnet()/splx() pair around netisr access in netintr()?

Some ports (alpha, arm, hp300) use splhigh() to protect netisr,
and other ports (sh3, sh5 etc.) use splnet().
Some other ports have no protect against netisr in netintr().
(of course if we can use atomic operation to clear netisr bits,
 no spl* protection is needed though)
---
Izumi Tsutsui
tsutsui@ceres.dti.ne.jp