In message <200304270501.h3R51UO09611@fearless-vampire-killer.waterside.net>, 
I had written:

-> 	While digging in that code I also found a bug in how we use the
-> 	R5k Page_Invalidate_S cacheop... The Rm52xx manual documents the
-> 	fact that CP0 TagLo must be zeroed before this operation (since
-> 	this cacheop just expands to a series of Index_Store_Tag opera-
-> 	tions internally); I also attach a fix for that.  I'm not 100%
-> 	sure if disabling all interrupts here is necessary, but figured
-> 	I'd better be safe so the TagLo register doesn't get reloaded
-> 	somewhere along the way with a non-zero value -- I'd especially
-> 	like feedback on this bit.

The same problem exists in arch/mips/mips/cache_r5k_subr.S; fixing these
two bits of code seems also to get the Intel GigE card (which would hang
at random times with what looked like incorrect RX/TX descriptors written
back to memory) working fairly well -- I'm doing a bunch of builds over
NFS to confirm that.

One last comment is that I need to re-confirm how many NOPs need to get
padded around the mfc0 and mtc0's, as the patch I sent last night seems
to be a bit light on those...

--rafal

----
Rafal Boni                                                     rafal@attbi.com
  We are all worms.  But I do believe I am a glowworm.  -- Winston Churchill