"Paul Koning" <pkoning@equallogic.com> said;

> What about MIPS processors with 40-bit physical addresses?  For those
> the PFN expands into the upper 32 bits, I assume.  (The MIPS PRA spec
> doesn't show it in the diagram though the text implies it.)

There are bunch of MIPS documents and implementations on earth.  It's
short to read only MTI definitions which are in fact selected collations
of design diversities.  Please refer to NEC's Vr10000 doco available 
online.  (much look like the original R10000 print)

R1x000 has FrameMask register which is assumed to manipulate EntryLo
in 36bit PFN compatible fashion.  It'd be useful when 40bit physical
address is not required by target hardware design.

Toru Nishimura/ALKYL Technology