> > Here's an attempt at a fix. This change reenables soft interrupts in
> > the UserGenException code, just after the return from trap()

Toru> I think the proposed code is not correct, and there is another
Toru> solution o fix the real issue there.

Toru> FRAME_SR contains the status register value when user processor
Toru> got an exception.  The SR contains;
Toru> - EXL bit is off,
Toru> - CU1 bit is on,
Toru> - IE bit is on,
Toru> - IM mask whose values as assigned at process initiation.

Toru> So, setting SR with the value there makes two bad things; to set
Toru> EXL condition and start FPU mistakenly.  These bits must be
Toru> turned off before MTC instruction updates SR.

The patch only uses the IM mask bits from the SR value saved in the
exception frame. The rest of the COP0 SR bits are preserved.


Toru> However, the real trouble is the way trap() is called.  It
Toru> tosses very confusing things about SR IE bit and IM mask.  Here,
Toru> I propose mine.

Toru> trap() is called in the following circumstance meats;
Toru> - turn off EXL condition (mandatory for processor)
Toru> - turn off CU1 bit (NetBSD requires)
Toru> - leave IE bit as it was. (it must be 1)
Toru> - If exception cause was T_BREAK, clear IM mask.  Otherwise,
Toru>   keep IM mask as it was.

Toru> ast() is called in the following condition;
Toru> - reset SR with FRAME_SR value minus EXL bit and CU1 bit.

You'll also need the KSU bits cleared in both cases. 

This sounds like it'll work.

- S