Subject: Re: port-mips/16154
To: None <port-mips@netbsd.org>
From: Toru Nishimura <locore32@gaea.ocn.ne.jp>
List: port-mips
Date: 11/23/2002 18:42:34
> Stephen Ma <stephenm@employees.org> said;
> 
> > Here's an attempt at a fix. This change reenables soft interrupts in
> > the UserGenException code, just after the return from trap() (note
> > that trap() will have already reenabled hard interrupts). The idea is
> > to allow any pending soft interrupts to run before returning to user
> > mode.

I think the proposed code is not correct, and there is another solution o fix
the real issue there.

FRAME_SR contains the status register value when user processor got
an exception.  The SR contains;
- EXL bit is off,
- CU1 bit is on,
- IE bit is on,
- IM mask whose values as assigned at process initiation.

So, setting SR with the value there makes two bad things; to set EXL
condition and start FPU mistakenly.  These bits must be turned off
before MTC instruction updates SR.

However, the real trouble is the way trap() is called.  It tosses very
confusing things about SR IE bit and IM mask.  Here, I propose mine.

trap() is called in the following circumstance meats;
- turn off EXL condition (mandatory for processor)
- turn off CU1 bit (NetBSD requires)
- leave IE bit as it was. (it must be 1)
- If exception cause was T_BREAK,  clear IM mask.  Otherwise,
keep IM mask as it was.

ast() is called in the following condition;
- reset SR with FRAME_SR value minus EXL bit and CU1 bit.

I think this change will straighten tangled trap()  and fix the issue Stephan
wanted to remove.

Toru Nishimura/ALKYL Technology