Subject: Re: port-mips/16154
To: None <port-mips@netbsd.org>
From: Toru Nishimura <locore32@gaea.ocn.ne.jp>
List: port-mips
Date: 11/22/2002 22:00:44
Stephen Ma <stephenm@employees.org> said;

> Here's an attempt at a fix. This change reenables soft interrupts in
> the UserGenException code, just after the return from trap() (note
> that trap() will have already reenabled hard interrupts). The idea is
> to allow any pending soft interrupts to run before returning to user
> mode.
>
> This change isn't necessary for the ps2, since that port doesn't use
> the processor's interrupts for soft interrupts, hence the #ifndef
> IPL_ICU_MASK.

The intent here is to make sure SR IM bits gets reset with "base level
interrupts to be served."   Although the Toshiba TX processor's SR
IM is different from standard ones, there is no need to place #ifndef as
long as the base level is set here as it was.  Need feedbacks from the
TX camp.

Toru Nishimura/ALKYL Technology