At Thu, 4 Jul 2002 07:56:04 +0000 (UTC), "Toru Nishimura" wrote:
> Due to the consideration for post-R4000's virtual address
> indexed cache, linear PTE array (whose contents == individual
> PTE) in KSEG2 space must be solely manipulated thru the
> range.

uh:

(1) there are "post-R4K" systems which do _not_ have dcaches indexed
    by virtual addresses.

(2) no, even for those processors, that just means that the
    arrangement of the VAs for the PTE pages and the VPT pages cannot
    cause cache aliases.  I.e., their virtual addresses must resolve
    to the same indices.


> L4/MIPS reports interesting researches on how 64bit address
> space TLB refill logic is implemented.  They made researches
> on several variants, and concluded it's effective to have software
> managed a TLB entry pool (cache) for a fast refill and fall back
> to longer path table-walk when the fast refill exception misses
> the target TLB entry.  Use google to fetch papers.

any particular search which would show those papers quickly?


cgd