Subject: Re: Support for MIPS32 and MIPS64 CPUs.
To: Takao Shinohara <shin@sm.sony.co.jp>
From: Simon Burge <simonb@wasabisystems.com>
List: port-mips
Date: 02/26/2002 23:35:19
Takao Shinohara wrote:

> You missed the point.

Yah, sorry, I totally misread what you'd said.

> I did not meant to say,
> 
> 	"Hey, you forgot 2way(3way) cache configs!"
> 
> My intention was, you need additional lines, such as;
> 
> 		cache_op_r4k_line(w2va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
> 		cache_op_r4k_line(w3va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
> 		cache_op_r4k_line(w4va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
> 		w2va += 16;
> 		w3va += 16;
> 		w4va += 16;

Thanks, I've fixed that up now.

Simon.
--
Simon Burge                            <simonb@wasabisystems.com>
NetBSD CDs, Support and Service:    http://www.wasabisystems.com/