Takao Shinohara wrote:

> > +void
> > +mipsNN_icache_sync_range_index_16_4way(vaddr_t va, vsize_t size)
> > [ ... ]
> 
> cache ops for other ways(2,3,4) are missing.
> 
> > +void
> > +mipsNN_icache_sync_range_index_32_4way(vaddr_t va, vsize_t size)
> > [ ... ]
> 
> ditto.

To date, all the mips32 and mips64 CPUs I've seen are 4-way associative.
The cache size detection code will panic if a CPU isn't 4-way.

The motivation for not including other way-sizes is code size.  At
the moment, you usually get mode cache ops that you really need (for
example, a MIPS32 CPU with 16 byte lines will get the 32-byte line cache
ops even though it can't use them) - we need to come up with a better
way of doing this.

Simon.
--
Simon Burge                            <simonb@wasabisystems.com>
NetBSD CDs, Support and Service:    http://www.wasabisystems.com/