> +void
> +mipsNN_icache_sync_range_index_16_4way(vaddr_t va, vsize_t size)
> +{
> +	vaddr_t w2va, w3va, w4va, eva;
> +
> +	/*
> +	 * Since we're doing Index ops, we expect to not be able
> +	 * to access the address we've been given.  So, get the
> +	 * bits that determine the cache index, and make a KSEG0
> +	 * address out of them.
> +	 */
> +	va = MIPS_PHYS_TO_KSEG0(va & mips_picache_way_mask);
> +
> +	va = trunc_line16(va);
> +	w2va = va   + mips_picache_way_size;
> +	w3va = w2va + mips_picache_way_size;
> +	w4va = w3va + mips_picache_way_size;
> +	eva = round_line16(va + size);
> +
> +	mips_dcache_wbinv_range_index(va, (eva - va));
> +
> +	while ((eva - va) >= (8 * 16)) {
> +		cache_r4k_op_8lines_16_4way(va, w2va, w3va, w4va,
> +		    CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
> +		va   += (8 * 16);
> +		w2va += (8 * 16);
> +		w3va += (8 * 16);
> +		w4va += (8 * 16);
> +	}
> +
> +	while (va < eva) {
> +		cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
> +		va += 16;

cache ops for other ways(2,3,4) are missing.

> +	}
> +
> +	SYNC;
> +}
> +
> +void
> +mipsNN_icache_sync_range_index_32_4way(vaddr_t va, vsize_t size)
> +{
> +	vaddr_t w2va, w3va, w4va, eva;
> +
> +	/*
> +	 * Since we're doing Index ops, we expect to not be able
> +	 * to access the address we've been given.  So, get the
> +	 * bits that determine the cache index, and make a KSEG0
> +	 * address out of them.
> +	 */
> +	va = MIPS_PHYS_TO_KSEG0(va & mips_picache_way_mask);
> +
> +	va = trunc_line32(va);
> +	w2va = va   + mips_picache_way_size;
> +	w3va = w2va + mips_picache_way_size;
> +	w4va = w3va + mips_picache_way_size;
> +	eva = round_line32(va + size);
> +
> +	mips_dcache_wbinv_range_index(va, (eva - va));
> +
> +	while ((eva - va) >= (8 * 32)) {
> +		cache_r4k_op_8lines_32_4way(va, w2va, w3va, w4va,
> +		    CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
> +		va   += (8 * 32);
> +		w2va += (8 * 32);
> +		w3va += (8 * 32);
> +		w4va += (8 * 32);
> +	}
> +
> +	while (va < eva) {
> +		cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
> +		va += 32;

ditto.

> +	}
> +
> +	SYNC;
> +}

--- Takao Shinohara