Thank you for your comments.
I've commited. Please check it.

updated files are:
    include/cache_r4k.h
    mips/cache.c
    mips/cache_r5k.c

----- Original Message ----- 
From: "TAKEMURA Shin" <takemura@netbsd.org>
To: <port-mips@netbsd.org>
Cc: <port-hpcmips@netbsd.org>
Sent: Sunday, December 16, 2001 11:40 PM
Subject: Vr4131 cache configuration


> Hi,
> 
> I'm working on NEC's new MIPS CPU Vr4131.
> 
> Vr4131 has 2-way set-associative cache though Vr4131's 
> processor revision number on COP0 is same as other 
> Vr41xx which has direct-mapped cache. So, you must
> distinguish Vr4131 from other Vr41xx in mips_config_cache().
> You can use highest bit of MIPS_PRID_REV field.
> 
> I've made the patch (attached). I'd like to commit the patch
> if no one objects.
> 
> Takemura