The great uncertainness clouding over my head for long time is how
cache machinary works when the target virtual address range is subject
to TLB miss.  ASiD/G is fine.  They would work as designed.
Apparently there are cautions, limitations and pitfalls around the case
cache insn encounters TLB miss.  Can anybody out there provide definitive
explanations about it?

Tohru Nishimura