On Fri, Jul 13, 2001 at 12:39:18PM +0900, Toru Nishimura wrote:

 > The great uncertainness clouding over my head for long time is how
 > cache machinary works when the target virtual address range is subject
 > to TLB miss.  ASiD/G is fine.  They would work as designed.
 > Apparently there are cautions, limitations and pitfalls around the case
 > cache insn encounters TLB miss.  Can anybody out there provide definitive
 > explanations about it?

In the case where you know you cannot access the address (i.e. address
is not KSEG0, not G, not current ASID), then you MUST use Index ops, and
the way to make this work is generally to get the significant index bits
out of the original virtual address, and then use that as an offset into
KSEG0.  That will hit the same indices, and not cause a TLB miss.

-- 
        -- Jason R. Thorpe <thorpej@zembu.com>