So, I really want to make the L2 cache on my Indy work, and thus
I need to rototill the way cache operations in NetBSD/mips work.

(This is something that needs to be done *ANYWAY*.)

Below is the comment describing how my new mips/include/cache.h works
(or, will work, once its fleshed out).  Everything is done via indirection.

Evenually, I want to include the pseudo-vector stuff suggested by cgd
and partially implemented by Chuck Cranor.  But I'd rather get *something*
working first, then deal with that level of optimization.

What I'm looking for here is comments on the primivites.

Thanks.

-- 
        -- Jason R. Thorpe <thorpej@zembu.com>

/*
 * Cache operations.
 *
 * We define the following primitives:
 *
 *	picache_inv_all		Invalidate primary I-cache
 *
 *	picache_inv_range	Invalidate primary I-cache range
 *
 *	pdcache_wbinv_all	Write-back Invalidate primary D-cache
 *
 *	pdcache_wbinv_range	Write-back Invalidate primary D-cache range
 *
 *	pdcache_inv_range	Invalidate primary D-cache range
 *
 *	pdcache_wb_range	Write-back primary D-cache range
 *
 * --- Secondary cache operations are optional:
 *
 *	sicache_inv_all		Invalidate secondary I-cache
 *
 *	sicache_inv_range	Invalidate secondary I-cache range
 *
 *	sdcache_wbinv_all	Write-back Invalidate secondary D-cache
 *
 *	sdcache_wbinv_range	Write-back Invalidate secondary D-cache range
 *
 *	sdcache_inv_range	Invalidate secondary D-cache range
 *
 *	sdcache_wb_range	Write-back secondary D-cache range
 *
 * There are some rules that must be followed:
 *
 *	I-cache Invalidate (all or range):
 *		If you have a mixed secondary cache, and you must
 *		perform an index operation, then you must perform a
 *		WB-Inv on the secondary cache.
 *
 *	I-cache Invalidate range:
 *		If you can't invalidate a range, you must invalidate
 *		the entire I-cache.
 *
 *	D-cache Write-back Invalidate range:
 *		If you can't WB-Inv a range, you must WB-Inv the
 *		entire D-cache.
 *
 *	D-cache Invvalidate:
 *		If you can't Inv the D-cache without doing a
 *		Write-back, YOU MUST PANIC.  This is to catch
 *		errors in calling code.  Callers must be aware
 *		of this scenario, and must handle it appropriately
 *		(consider the bus_dma(9) operations).
 *
 *	D-cache Write-back:
 *		If you can't Write-back without doing an invalidate,
 *		that's fine.  Then treat this as a WB-Inv.  Skipping
 *		the invalidate is merely an optimization.
 *
 *	All operations:
 *		Valid virtual addresses must be passed to the
 *		cache operation.
 *
 * Finally, these primitives are grouped together in reasonable
 * ways.  For all operations described here, first the primary
 * cache is frobbed, then the secondary cache frobbed, if the
 * operation for the secondary cache exists.
 *
 *	mips_icache_inv_all	Invalidate I-cache
 *
 *	mips_icache_inv_range	Invalidate I-cache range
 *
 *	mips_dcache_wbinv_all	Write-back Invalidate D-cache
 *
 *	mips_dcache_wbinv_range	Write-back Invalidate D-cache range
 *
 *	mips_dcache_inv_range	Invalidate D-cache range
 *
 *	mips_dcache_wb_range	Write-back D-cache range
 */